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| HV302DB1 Hotswap Controller Introduction The Supertex HV302DB1 demo board contains all circuitry necessary to demonstrate the features of the HV302 hotswap controller. Intended primarily as a negative hotswap controller, the HV302 controls the negative supply path. Four sequenced power-good signals are provided, with timing controlled via 3 resistors. Included on board is a 100+F capacitor to provide a capacitive load for testing. Additional capacitance may be connected to the VOUT terminals. Or the 100+F may be removed altogether The board may be modified to meet custom requirements. Instructions are provided on the next page for modifications. Specifications Input Voltage Inrush Limit Circuit Breaker Trip Retry Interval On Resistance Undervoltage Trip Overvoltage Trip Power Good Signals PWRGD A PWRGD B PWRGD C PWRGD D 10V to 90V 1A 20% 6.7A 20% 16sec typ 40m 8 max 38.0V on, 32.2V off 64.5V on, 70.0V off Active High ~5ms after CLOAD charged ~200ms after `A' ~100ms after `B' ~5ms after `C' Board Layout and Connections R10 R9 HV302 R8 R4 C3 C1 C2 R6 R7 C4 R5 Q1 C6 + enable + enable + enable + enable DC/DC Converter - last enabled DC/DC Converter - DC/DC Converter - DC/DC Converter - first enabled VIN VIN Connect the supply voltage to these terminals. Supply voltage may range from 10 volts to 90 volts. A high source impedance may cause oscillations when the input voltage is near the undervoltage trip point. A high source impedance results in a large voltage drop when loaded, causing undervoltage lockout to kick in, disconnecting the load. With the load removed, input voltage rises, causing undervoltage to release and reconnecting the load. The cycle repeats, resulting in oscillations. Source impedance must be less than the following to avoid oscillations: reason, DC load at start-up should be less than 900mA. Note that DC start-up load limitation decreases with added load capacitance. Connecting additional load capacitance alters the inrush current limit. See the HV302/312 data sheet for details. PWRGD Connect to the power supply's ENABLE inputs. Depending on the power supply, it may be necessary to level-translate this signal via opto-isolator or discrete circuit. Refer to the HV302/312 data sheet for a description of PWRGD and related application circuits. PWRGD is an open-drain output. During start-up and whenever VIN is lower than the undervoltage trip point or greater than the overvoltage trip point, PWRGD is pulled down to VIN-. Once VIN is within the proper range and the load capacitance has fully charged, PWRGD assumes a high impedance state. RSOURCE < 3V I LOAD VOUT Connect the power supply or other load to these terminals. VOUT+ is connected to VIN+, it is VOUT- that is switched. Application of a DC load during start-up extends the time inrush limiting is active. If this time exceeds 100ms, the HV302 shuts off, retrying as quickly as 12s later. For this rev 0 21MAY021 1 HV302DB1 Schematic VIN+ 14 Hotswap Controller VOUT+ VDD R1 487k R2 9.09k R3 9.09k 6 UV OV VEE 7 PWRGDA PWRGDB PWRGDC PWRGDD TB TC TD 4 3 2 1 HV302 11 12 13 R8 121k C5 not used R9 60.4k 5 RAMP 10 SENSE 8 GATE 9 R10 3.01k C6 100+F R4 not used C1 10nF C2 not used C3 680pF R7 not used R6 0 VINR5 15m C4 not used Q1 IRF3710S VOUT- Inrush Limit As supplied, the inrush current limit is set at 1 amp. To set inrush limit to another value, please refer to the HV302/312 data sheet. The circuit breaker trip point is set at 6.7 Amps. To set at a different level, change R5 according to the following equation: Circuit Breaker Transient Immunity The HV302 has built-in transient immunity of 2-5+s. To increase transient immunity, an RC low-pass filter (R6C2) may be placed on the SENSE input. (The demo board is supplied with no filtering.) Be aware that filtering the sense input will cause the inrush current limit to overshoot at turn-on - the greater the filtering, the greater the overshoot. I CB = 100mV R5 Undervoltage/Overvoltage Lockout Resistors R1, R2, and R3 set the undervoltage and overvoltage trip points. New trip points may be programmed by changing the values of these resistors. Refer to the HV302/312 data sheet for more information. The power rating of R5 should be selected based on maximum current during normal operation, which could be just under the circuit breaker trip point. P5 = 100mV I CB Additional Components The RC network (R7C4) across the gate-source of the external FET provides control loop compensation which prevents inrush current peaking. If the PWRGD A signal is used and experiences large voltage swings, a 10nF capacitor should be installed at C5. This limits dV/dt which may otherwise cause undesirable coupling to internal circuits. To defeat the circuit breaker auto-retry, install a 2.4M resistor at location R4. For servo-mode inrush control, remove C3. Inrush limit will then be 3.3 Amps. See the HV302/312 data sheet for details. Timing Timing capacitor C1 determines start-up delay, rise time, and circuit breaker retry interval,. Changing C1 will alter these timings. Refer to the HV302/312 datasheet for the equations that relate these timings to the value of C1. For use in the equations, the nominal gate threshold voltage (VGS) of the supplied IRFR3710 is 3V and transconductance is about 10 siemens. Resistors R8, R9, and R10 set the delays for PWRGDs B, C, and D according to the following equation: t D = 1.67F R X rev 1 24MAY02 2 |
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